1. Field of the Invention
The present invention relates to a transistor structure and a method for fabricating the same, particularly to a suspended nanochannel transistor structure and a method for fabricating the same.
2. Description of the Related Art
Theoretically, a common semiconductor element can have a subthreshold swing (SS) of 60 mv/decade optimally. Thus, SG-MOSFET (suspended gate MOSFET), which integrates MEMS (Micro Electro Mechanical System) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor), has been developed to achieve a better SS and a higher on/off current ratio, wherein the suspended gate structure provides adjustable gate capacitance to break through the theoretical SS limit and achieve a SS value of several mv/decade. However, the microelectromechanical structure thereinside increases the dimensions of the element (usually several to tens microns), and the larger dimensions of the element increase the difficulty of the etching process for fabricating suspended gates.
In a paper “IT MEMS Memory Based on Suspended Gate MOSFET”, IEDM 2006, N. Abele et al., proposed a MEMS memory, which is based on a planar structure and a microelectromechanical process, wherein a selective dry etching process removes a sacrifice dielectric layer to form an air gap between the gate and the channel. However, in this prior-art, what is suspended is not the channel but the gate. Because of the planar structure, the air gap is very hard to fabricate, and the etching for the air gap must be undertaken with a selective dry etching process. Because of the difficulty of fabricating an air gap from the sacrifice dielectric layer, the fabricated air gap has a considerable thickness (more than 200 nm). Thus, the element has to use a very high operating voltage. A Taiwan patent No. 246541 disclosed a method for mass-fabricating a low-cost silicon nanowire, wherein a sensitizing agent and an activating agent catalyze the surface of a silicon substrate and enable metal atoms to adhere to the surface. Next, the silicon substrate is soaked in an acidic electroless plating liquid to form thereon a metal layer -containing catalytic metal particles. Next, the silicon substrate is placed in a high temperature tube furnace; then, the catalytic metal particles and the silicon atoms on the interface form a liquid silicide alloy. Because of the temperature gradient in the SLS (Solid-Liquid-Solid) chemical synthesis process, the silicon atoms are rearranged to form silicon nanowires by the catalytic effect. Although the prior-art patent can mass-fabricate silicon nanowires, it still has problems of alignment and pollution of residual catalytic metal.
In a paper “Very High Frequency Silicon Nanowire Electromechanical Resonators”, Nano Lett., Vol. 7, pp. 1953-1959 (2007), X. L. Feng et al., used a VLS (Vapor-Liquid-Solid) process to fabricate suspended nanowire elements and studied the resonance performance thereof to evaluate the feasibility of functioning as a resonator. The prior art is a laboratory approach and hard to position and align the nanowires. Therefore, it is unsuitable for mass production. Besides, the nanowire element is a passive element because it has only a source electrode and a drain electrode.
Accordingly, the present invention proposes a novel low-voltage suspended nanochannel transistor and a method for fabricating the same to simplify the fabrication process, reduce the cost, overcome the conventional problems, and provide a better MEMS MOSFET.